By: Karan Gill
1. Overview
This page provides a high-level insight into a previous system I developed: electronics hardware system of a next-generation Fused Filament Fabrication (FFF) 3D Printer. In this portfolio, I will go over my design approach from inception to completion.
2. Introduction
There are several different technical projects I’ve undertaken that have involved developing systems using electromechanical devices, algorithms, and electronics hardware. But the most memorable one was the development of the hardware electronics of a Fused Filament Fabrication (FFF) 3D printer from the ground up. My responsibility was to execute the entire project that included product concept development, product management, research, hardware architecture, component selection, schematic design, board layout, manufacturing and debugging.
3. Project Motivation
The company was initially selling a 3D printer based on open-source hardware (electronics and firmware). There were some issues with the product: features lacking in the system and it was difficult to develop on the existing platform for future iterations of the product. Since the new printer was being developed from the ground up, we had an opportunity to develop proprietary firmware, which would give greater developmental control to the engineers within the company.
4. Concept Development
I initiated the project by defining the basic vision of our ideal next-gen 3D printer (and had iterative discussions with the CEO). I went with the following requirements in mind when researching, developing the architecture, and performing component selection:
– State-of-the-art technology and future proof for at least 5 years
– Scalable and expandable platform with new technologies such as a camera (for monitoring prints), heated platform, robotic print remover in future, and other developing technologies.
– Provides a better user experience by being more reliable, easier to use, and incorporating useful newer technologies
– Easy to assemble and troubleshoot for production workers (keyed connectors)
– Cost-effective
In addition to what’s already implemented in the previous generation 3D printer, we agreed that the new design should include the following technologies:
– LCD touchscreen for better UX and 3D model previews
– Wireless/ethernet network functionality
– Auto-bed leveling (extension of a previous project that I developed)
– Better print quality using more computationally intensive calculations for driving motors
– Accelerometer sensor for real-time mechanical feedback
– Filament detector
– Custom motor controllers for better thermal dissipation and greater firmware-level control
– A power system that resumes printing in event of a power failure/accidental shutoff
– The hardware also had to comply with FCC class B certification
5. Research and Architecture
The architecture process was initiated by searching for an appropriate CPU or Microcontroller (MCU) that was going to form the core of the system. The MCU used in the older system was Atmel’s Atmega 2560, a legacy technology in the modern age. After some searching, the choice was clear: to choose a CPU or MCU with ARM architecture, as it has the highest performance for the power consumption in the lower cost range. Other newer 3D Printers were also using this architecture in their system. Performance of the CPU is particularly important in this design because of the addition of the LCD touchscreen and Wi-Fi/networking capabilities. The addition to the LCD, the system also needed additional RAM to store and draw frame buffers.
The decision to go with an ARM Microcontroller (MCU) over a CPU was made due to the integration of a greater number of peripherals in a single package. Most ARM Cortex- M MCUs from different OEMs (ST, Freescale, TI, NXP, Atmel) had different peripherals integrated at various quantities. One of the most important and expensive peripheral that was needed was the LCD Controller that can drive a fairly high-resolution 24-bit RGB LCD directly from the MCU. Ultimately, we decided to go with STM32F746NGH6 ARM Cortex M7 Microcontroller (at the time, fastest available in the market), which also has all the peripherals we need including the LCD controller.
Another important architectural decision was made to address a shortcoming of the previous 3D printer, which would exhibit a strange printing behavior: when the user manipulated the interface on the screen, the printing speed would significantly decrease and then resume back to full speed when the user stopped interfacing with the printer. The problem was that only one processor was allocated for 2 very different tasks: interface and printing. This resulted in the CPU processing time being taken away from the Printing module when the user interface was fully engaged, thus resulting in insufficient resources for performing math calculation to drive motors. This issue was one of the inspirations for an application-specific dual processor architecture (figure 1) that would allow the interface and printer firmware modules to run independently on two different processors. To implement this, we allocated one STM32F746 MCU to handle the interface with various aspects of the computer system of the printer (LCD, Wi-Fi/network, NAND Flash, USBs, SDRAM, ornamental LED lights) and another STM32F746 to take care of tasks specific to 3D printing (such as actuating motors, endstop hardware interrupts, fans, heater, thermistor, filament detector).
5.1 Market Search for Components
After laying out a high-level architecture and finalizing the MCU, I searched the market for other major components in the system.
Additionally, I also consulted with field engineers for the latest solutions available from electronics sales companies, such as Arrow Electronics and some manufacturers in China. Digikey and Mouser were instrumental in the component search and helping build the Bill of Materials (BOM). The overall budget, performance requirements, market availability, period of guaranteed availability, and ability to replace generic components in the design were some of the factors taken into consideration while performing the search.
Some of the important components that I was searching for were:
– LCD (TFT Display) touchscreen: I rigorously tested various displays for their quality (color accuracy, contrast brightness, white levels, uniformity, color shift, burn-in, edge light leak, reflectivity) and size.
– Storage IC: NAND Flash was a more suitable choice for our system as it was more in line with our size requirements and had various interfaces available in a greater variety. eMMC (SDMMC) interface was chosen, as other interfaces required the engagement of the Flexible Memory Controller (FMC) that was being used to interface with SDRAM.
– SDRAM: The MCUs had a small amount of SRAM which had to be supplemented with external RAM. 32-bit SDRAM was chosen for one of the MCUs, which was required especially for the purpose of storing/drawing LCD frame buffers. Additionally, it was used for networking and calculation data storage as well.
– Wi-Fi module with an external antenna attachment.
– Ethernet PHY with direct RMII interface to the Wi-Fi module (as all RMII interface pins were being occupied by the main MCU).
– LED backlight driver for LCD display.
– Power system components: Voltage regulators (switching and linear), backup power modules.
– Stepper motors and controllers.
– Specialized keyed connectors and high-current connectors for interfacing with the other boards and electronics in the system.
5.2 Bill of Materials
As the components were being finalized and implemented in schematics, I constructed the Bill of Materials (BOM) which included: designator, description, whether it’s mounted, quantities, size (for SMD components), manufacturer, manufacturer’s part number, supplier, supplier part#, alternative supplier part #, unit price, total price.
5.3 Diving deeper into Architecture and Pin Selection
To finalize the architecture and initiate the schematic design, I went over the microcontroller’s datasheet, hardware development application note, and other documents in detail.
To allow other major components to interface with the MCUs, pin selection was the key step for effectively architecting the system before initiating the schematic design. One of the challenges was that the same MCU pins could be used for different peripherals (such as LCD, SDRAM, and SPI). To resolve this, I allocated the pins in a way where all the required peripherals could be connected without occupying conflicting pins. Additionally, I also had to plan for the availability of interfaces that may be required in future iterations (without rearchitecting the entire MCU).
To execute pin selection, I used two tools: STM32CubeMX (a software made by the manufacturer to allow pin selection for various interfaces) and Alternate Function Mapping tables in the datasheet.
While selecting pins for abundant peripherals on the MCU, such as I2C, SPI, and timers, their specifications had to be best matched with the requirements of the interfacing device/IC (such as speed requirements). For example, SPI1 could provide a greater speed than SPI2, for applications such as Wi-Fi interface, SPI1 would be preferred over SPI2).
More importantly, peripherals had to be selected accordingly to the available Direct Memory Access (DMA) stream channels, which would allow a peripheral continuous access to memory without the intervention of the CPU core (so the CPU resources are left free for other operations).
5.4 Information from Datasheets
As I was approaching full execution of the schematic design, I went over datasheets of major components such as SDRAM, LCD, Wi-Fi, NAND flash, etc. Datasheets provided crucial information regarding the components, including:
– Description of operation
– Signal descriptions and pin assignments
– Electrical characteristics, constraints, and tolerances
– Power supply requirements
– Mechanical and thermal characteristics, constraints, and tolerances
– Package information for designing footprints and schematic symbols
– Special PCB layout guidelines
6. Schematic Design
I manually designed the footprints and schematic symbols of components (observed in datasheets), as Altium lacked many of the components in their library. Interestingly, a failure, which will be discussed later, that occurred in the first prototype was because of a faulty footprint from Altium library (designed by manufacturer).
The hardware development application note by ST Microelectronics was instrumental in kickstarting the schematic design. It provided necessary development-oriented information such as power supply scheme, bypass capacitor requirements/placements, crystal oscillator recommendations, reference schematic, layout recommendations, high-speed design requirements such as impedance control and length matching for relevant interfaces, etc.
While carefully going through the signal descriptions and pin assignments section in the datasheets of major components, I carried out the schematic design in a very standard way: allocate one sheet per major component (i.e. SDRAM). In total, there were 26 schematic sheets for the system. Netlabels and ports of the same name were used to interlink schematics within different sheets.
Implementing design rules for the PCB layout phase commenced in the schematic design phase. Net Classes were made for specific groups of signals that required routing according to certain guidelines (i.e. length matching). It also allowed convenient color-coded viewing of signal groups in the layout mode.
After all the schematics were completed, I proceeded to the high-speed layout phase of the PCB. The following section describes the high-speed mixed-signal board design in greater detail.
7. PCB Design: High-Speed Mixed-Signal board design
This section provides a high-level overview of PCB design decisions and layout for a motherboard that acted as the central hub for the other 5 PCBs in a 3D Printer system. The size of this board was 16.4 cm x 12 cm.
7.1 Layer Stack
Figure 6 shows a 10-layer stack scheme used for a board that contains two ARM Cortex-M7 Microcontrollers, 32 Bit SDRAM, along with many other components. Usually, a greater number of layers allows a greater degree of freedom in routing and signal integrity/EMC optimization, as the signals can be better isolated and shielded by planes. However, one major factor in deciding to go with a lower number of layers is cost. Before choosing the appropriate layer stack, I contacted manufacturers and discussed various aspects of the layer stack and many other factors that would affect the prototype and mass-production cost in Taiwan and China. Although a 10-layer stack may have seemed to be a bit excessive, there was an insignificant cost difference as compared to a lower number of layers, especially when mass-manufactured.
Along with the layer stack, drill pairs were configured, which included through-hole vias and microvias.
The layer stack in figure 6 can be visualized as a symmetrical sandwich. Layers L1-L5 exhibit the same properties and encompass similar signals as compared to layers L6-L10:
– L1 housed lower frequency and steady-state signals, including high current from stepper motor drivers.
– L2 and L4 are ground planes not only act as a stable uniform reference but also allowed an uninterrupted return path for the high-speed signals routed on L3. Additionally, they provide EMC shielding for the relatively sensitive high-speed signals on L3. Note: Although L2 “Type” in figure 6 does not appear to be a ground plane in the layer stack table, a polygon pour was used to allow for microvias to carry the signals from BGA packages to inner layers.
– L5 is a power plane used to deliver multiple voltages (from digital electronics to high current stepper motor drivers and heater). It was retracted from the board edges by 20H (h=distance to adjacent plane) to minimize EMI.
– L6-L10 are allocated symmetrically to L1-L5.
7.2 Design Rules
Design rules such as clearance constraints, routing width, via styles, differential pairs routing, length matching constraints, solder mask expansion, polygon pour rules, routing angle, hole size, hole to hole clearance, board outline clearance were created. A minimum clearance of 5 mils was used to route traces.
7.3 Component Placement
Figure 7 illustrates an overview of all 10 layers (polygon pours and power planes are removed for better viewing) of various sections of the mixed-signal board. The white box houses high-speed electronics and signals, yellow is relatively lower speed, and the red is mostly power. High-speed components were kept at a distance from high-power components to minimize coupling EMC issues. Decoupling capacitors were placed on the opposite sides of MCU and SDRAM, to minimize the imposed series inductance. Connectors were placed accordingly to allow easy connections during assembly while in the casing.
7.4 PCB Routing
In figure 7, the white box is an area of the board where the majority of the signals were routed using high-speed design principles: length matching, impedance control, crosstalk minimization, optimizing signal return path, optimal differential routing, and providing a high-quality capacitor placement for stable operation and minimizing EMI. For calculating variables such as the minimum distance between signals to avoid crosstalk, single-ended/differential impedance, via impedance and current capacity, I used the Saturn PCB Calculator as described in a later section. The design also took other factors into consideration such as routing signal groups by the same topology, keeping an appropriate geometry of the serpentine waves, using stitching vias, avoiding 90-degree angles, stubs, and routing close to the edge, etc.
When designing for even higher speeds, the design constraints become significantly tighter as the rising edge of the signal becomes faster. Ultra-high-speed design would also need consideration of more parameters such as changing dielectric constant w.r.t. signal speed, greater influence of board capacitance (therefore limiting routing length), via design, more simulations to be used, and also more test points to analyze signal integrity on an oscilloscope during testing.
7.4.1 Fanout
Fanout of the microcontrollers and other high-density BGA packages was the first step when routing this PCB. I used through hole and microvias for manually fanning out the signals to internal and bottom layers. It was imperative to keep an appropriate clearance of vias (especially through-hole vias) with decoupling capacitors on opposite sides of ICs.
7.4.2 PCB Routing Planning
One of the main aspects of planning to route the PCB is to determine how the signals are going to be routed and fanned out in high-density areas while complying with high-speed design rules. For example, signals connecting the MCU and SDRAM should be routed in groups, ideally, with the same topology. Initially, an iPad and stylus were used to plan the signal routing to get a general sense of how groups should be routed relative to each other.
7.4.3 High-Speed signal routing
As an example from this design, the SDRAM required about 50 signals to be routed. There were several groups of different kinds of signals. These were first organized in net classes in the schematics for allowing the creation of specific design rules in the layout mode. Signals within the same data group could be closer together since their state would be simultaneously changing and were being latched at the same time (crosstalk is less of an issue). However, greater distance was allowed in different groups such as different data and address groups to minimize crosstalk. As observed in datasheets, there were specific length matching constraints for intergroup routing and between all the groups w.r.t. clock signal. Additionally, all traces needed to have an appropriate width in their respective layers to achieve an impedance of 50 Ohms. Similar design rules constraints were applied for various peripherals and interfaces such as eMMC, LCD, SPI, and differential signals.
Analog signals going from the edge of the board to the ADC on MCU were kept in great isolation from digital signals.
Signal integrity and EMC go hand in hand. If a board is developed using good design principles while taking signal integrity into consideration, it is less likely to have EMC issues because majority of the energy in the signals is effectively transmitted from origin to destination instead of being radiated to its surroundings or into other signals. Shielding using ground planes and metal shields is another step to improve electromagnetic susceptibility.
Looking back at the image of the entire PCB in figure 7, the yellow box mostly contains lower speed signals, which includes a Wi-Fi module that’s commutating via UART to the ARM MCU. There is also an ethernet and USB for connectivity. The Ethernet PHY and RJ45 jack are connected via analog differential signals.
The red box in figure 7 contains mostly high-power routing which includes stepper motor drivers, heater, and LED strip. The area where it reads X, Y, Z, E (as marked in the silkscreen) house the custom-made pluggable stepper drivers, which I architected and designed prior to this board. It’s important to note that the isolation of high-speed digital electronics from high current electronics is essential because that allows for better isolation of noise in the traces and minimizes coupling, which optimizes signal integrity and EMC.
7.4.4 Design Calculations
Much of the calculations for the board routing, including the high-speed signals were done using a very handy tool: Saturn PCB Toolkit. It’s a tool used for calculating various parameters that are vital to good PCB design such as minimum distance required between traces to avoid a high level of crosstalk, conductor width to achieve a certain impedance. It also helped me find the optimum dielectric thickness to allow impedance-controlled routing while minimizing crosstalk. Behind its interface, it implements complex crosstalk, impedance, and current equations.
7.4.5 Thermal design considerations
The thermal design for most ICs was relatively straightforward due to their low current requirements. There were copper pads made on the opposite side of the board for some ICs for heat dissipation, as instructed in their respective datasheets. ICs such as ethernet PHY, Wi-Fi module, and some other power ICs have their own copper pads (after removing the solder mask layer).
The most significant thermal design consideration was when designing a 4-layer custom stepper motor driver/controller. The driver IC was made to conduct heat to the entire layer on the outside with the solder mask removed. The drivers were located immediately above a cooling fan to allow for active cooling. The airflow was being sucked from the bottom, through the stepper drivers, and through a vent from the top/side of the machine.
7.4.6 Finishing the Layout
To finalize the PCB routing, I performed length matching and ran the Design Rule Check, clearing out the errors one by one. Moreover, I visually checked all the connections and polygon pours before generating the manufacturing files. Silkscreen was added which made the assembly more intuitive for the board and 3D printer.
7.5 Manufacturing the PCB
The board was designed with mass production in mind and was designed be cost-effective. I was in touch with board houses from the U.S., Taiwan, and China to get a good idea of cost effective design constraints that I had to implement when designing the PCB. When the PCB was finished, all the Gerber, drill, pick and place, bill of materials files were submitted to a manufacturer in Taiwan that operates in the U.S. We ordered 2 fully assembled PCBs for testing.
7.6 Verification and testing
When we received the boards, they were thoroughly inspected and tested. The more sophisticated components such as the MCUs, SDRAM, and LCD touchscreen were tested with custom firmware developed by the firmware engineer. The design was completely functional first time and it was a relief that the first prototype could pretty much go into production with this PCB until we found that one of the power components had shorted. It turned out that one of the footprints from Altium library was defective and shorted a section on the board. A valuable lesson was learned: double-check someone else’s work before implementing it in your own. A system is only as robust as its weakest link. Fortunately, the correction to the design was minor.
8. Conclusion
This technical portfolio covered the development, from inception to completion, of all the internals of the next-gen 3D printer that took about 10 months.
The PCB covered in previous sections was the core of the electronics system and had to be connected to five other peripheral PCBs, each with their own functionality.
If I were to go back and make improvements to the design process, I would design the motherboard prototype in modules, instead of designing it on one PCB, as the firmware engineer can begin developing and testing for our system without any waiting (especially in the absence of a dev kit). Another benefit is that it’s easier to catch and isolate failures and iterate on a modular design. However, it may increase the hardware development time as there’s a reiteration required to finally package the modules into one PCB.